The interface between an integrated circuit and external circuitry is commonly a large complementary metal-oxide-semiconductor (CMOS) inverter as shown in FIG. 1. This circuit, known as an output driver or output buffer driver, drives a capacitive load, C.sub.L, that may comprise a data bus and circuits attached thereto. The design of the output driver is constrained by the requirement that it charge and discharge the load capacitance quickly enough to transmit a signal within a short time, but not so short a time as to generate a current spike that may upset the performance of circuits sharing the same bus as the output driver. Assuming that the load capacitance is charged to power supply voltage level VDD, and the load is discharged by the output driver through inductance L, which may include package and bus inductance, the noise voltage generated is LdI(t)/dt. Hence, the noise generated by the driver is proportional to the slope of the curve (the slew rate) that describes the discharge current of the capacitive load. A typical discharge current curve is shown in FIG. 2. A discharge curve with a steep slope generates more noise than for a shallow slope, but a discharge with a shallow slope requires more time for completion. The rate at which the output driver functions is thus a tradeoff between the increased noise of a rapidly charged or discharged load and the slower signal transmission of a slowly charged or discharged load.
It is also desirable that the output driver provide alternative modes of operation, such as standby or sleep modes. In the standby mode of operation for a flash memory output circuit, for example, the output driver is disabled (tri-stated) and the output data bus is not driven. In standby mode the output driver should consume as little current as possible. In the sleep mode, the output driver is designed to draw little current, but the data bus is still driven with the data corresponding to the last address requested by the user. The sleep mode is entered after a certain period of time elapses after the last address request. Thus, not only must the output driver be designed to operate at a given slew rate in its active mode, but also to provide very low power modes as well.
Past efforts at controlling the charge or discharge rate of an output driver have relied on a reference voltage generator to control the rate at which the driver is driven to either a logic high or a logic low. These circuits typically consume significant current in both the active and standby modes in order to ensure that the output settles quickly to its final level after the transition of the circuit from the standby state to the active state. The high current consumption is due to the use of high-impedance bleeder circuits, which consume current to maintain the reference level close to the desired level. See, e.g. U.S. Pat. No. 4,614,882 to parker et al., U.S. Pat. No. 5,300,828 to McClure, and U.S. Pat. No. 5,489,862 to Risinger et al. Current is also consumed in circuits designed to maintain intermediate nodes within the output circuit at voltage levels close to the active-state levels when the circuit is in standby mode.